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Fault isolation with ‘x’ filter for bogus signals and intensive scan cell sequence validation / Khor Wooi Kin

Fault isolation with ‘x’ filter for bogus signals and intensive scan cell sequence validation_Khor Wooi Kin_E3_2017_MFAR
Kebimbangan muncul apabila data silikon dikumpul dengan menggunakan Design-For-Test (DFT). Isyarat yang mengandungi nilai ‘x’ dalam simulasi, disebabkan oleh sintesis logik yang rumit dan nilai asal apabila diaktif, sering mengelirukan proses kegagalan pengasingan dengan situasi gagal yang palsu. Selain itu, sel skan dalam rantaian skan juga mempunyai nilai yang berbeza antara data silikon dan data simulasi disebabkan oleh fail pemetaan yang bukan ideal dari kumpulan pereka. Oleh itu, pembangunan alat yang bersepadu dan dapat menapis isyarat mengandungi ‘x’ dalam talian serta mengesahkan korelasi antara data silikon dan data simulasi dengan liputan sekurang-kurangnya 90% adalah sangat penting. Data mikropemposes Intel sebenar dari generasi ke- 6 dengan 14 nm teknologi proses diimport untuk memastikan aplikasi tesis ini dalam industri. Alat keperluan seperti “Differentiate and Display” fungsi yang memudahkan data analisis, operasi DAN get logik yang menapis isyarat ‘x’ serta XOR get logik yang mengendalikan kebalikan isyarat dicipta dalam tesis ini. Keputusan Menunjukkan alat penapisan isyarat ‘x’ yang dibangunkan berjaya dan liputan minima alat pengesahan ialah sekurang- kurangnya 96.50%. Kes penggagalan keasingan dalam industri diimport dan perbezaan prestasi sama ada dengan alat yang dibangunkan atau tidak dibandingkan. Keputusan ujian optik yang tidak menyakinkan diperolehi apabila alat yang dibangunkan tidak diguna. Manakala, kegagalan litar pintas antara via dengan lapisan logam didapati selepas penggunaan alat yang dibangunkan dalam tesis ini. Kesimpulannya, tesis ini telah mencapai semua objektif yang ditentukan. There are some concerns in silicon data collection by using the Design-For-Test (DFT). Bogus signal which carries ‘x’ value in simulation, results from the complex logic synthesis and power-up floating state can often mislead the fault isolation process with invalid failing condition. Besides, scan cells within the scan chain architecture is also having mismatch value in between the simulation data and silicon data due to the non-ideal mapping file passed down from the designer team. Hence, it is important to develop an integrated tool that can filter all the bogus signal online and to validate the correlation between silicon data and simulation data with minimum coverage of 90%. Data from actual Intel 6th generation microprocessor with 14 nm process technology, Skylake is imported to ensure that the application of this thesis in the current industry market. Necessary tools such as the “Differentiate and Display” feature to ease the analysis of data, the AND-logic operation to filter the bogus signal and X-OR logic operation to handle the inverted characteristic of signals are developed throughout the thesis. Results show that the developed integrated filter of bogus signals is successful and the minimum coverage of validation tool is 96.5%. Actual failure analysis case from industry is imported and the difference with and without the developed tools are compared. Inconclusive optical test result from the sample is obtained without the implementation of tools. On the other hand, defect of short circuit between the via and the metal line is found after the implementation of the developed tools. It is concluded that this thesis has achieved all the objectives set.
Contributor(s):
Khor, Wooi Kin - Author
Primary Item Type:
Thesis
Language:
English
Subject Keywords:
Design-for-test (DFT) ; design for testability (DFT) and design for debug (DFD) , DFx feature
Sponsor - Description:
Pusat Pengajian Kejuruteraan Elektrik & Elektronik -
First presented to the public:
8/1/2017
Original Publication Date:
3/30/2018
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 93
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2018-03-30 10:33:28.0
Date Last Updated
2020-05-29 17:19:51.66
Submitter:
Mohd Fadli Abd. Rahman

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Fault isolation with ‘x’ filter for bogus signals and intensive scan cell sequence validation / Khor Wooi Kin1 2018-03-30 10:33:28.0