(For USM Staff/Student Only)

EngLib USM > Ω School of Electrical & Electronic Engineering >

Drrii sdram stressing and validation algorithm (intel)

Drrii sdram stressing and validation algorithm (intel) / Chuah Siang Chun
DDRII SDRAM berfungsi sebagai memori dalam suatu komputer. Ia digunakan sebagai tempat penyimpanan maklumat dalam bentuk nombor binari iaitu 0’s dan 1’s. Dalam era perkembangan teknologi yang begitu pantas hari ini, frekuensi memori juga menaik dengan kadar yang amat cepat. Untuk memastikan memori komputer adalah sesuai dengan suatu sistem, satu program yang bernama MSTRESS telah direka. Program ini direka untuk memastikan masa isyarat adalah tepat dan mengesahkan memori dapat menyimpan dan mengeluarkan maklumat yang tepat. Malangnya, algoritma program ini tidak disimpan rekod semasa ia direka. Sebab itulah, kajian ini telah dijalankan untuk mencari algoritma pengesahan and penekanan memori program ini.Untuk memahami algoritma program ini, pengetahuan asas tentang memori dan cache perlu dibelajari terlebih dahulu. Selepas itulah baru mulakan pembacaan dan pemahaman script program. Selain daripada itu, ujian praktikal juga perlu dijalankan supaya dapat mengesahkan program tersebut berfungsi sepadan dengan ia direka. Akhirnya, melalui pemahaman script dan ujian praktikal, ia mengesahkan bahawa program tersebut dapat mengesahkan data dan memastikan masa isyarat memori adalah tepat. Algoritma tersebut dapat memastikan memori tersebut adalah sesuai dengan sistem tersebut. _______________________________________________________________________________________________________ DDRII DRAM functions as the computer’s memory in a computer system. It is used to store information in binary which is 0’s and 1’s. The speed of the memory has increased rapidly because of the fast technology development. In order to verify the memory is compatible or able to use in the system, a test called as MSTRESS has been developed. The program is designed to stress and validate the memory to make sure the memory is working in the right timing and do not give invalid or wrong data. Unfortunately, the algorithm and the flow of the program are not recorded. A study through the program source code is needed to understand the algorithm. To understand the algorithm of the program, the fundamental knowledge of memory and cache has to be studied. Then, reverse engineering through the source code of the program will be done. Other than that, tests are carried out to validate the program. Through the careful studies and test, it shows that the algorithm of program is capable to stress and validate the memory in a computer system. The algorithm is able to ensure that the data mismatched do not happen and the timing of the memory is compatible to the system.
Contributor(s):
Chuah Siang Chun - Author
Primary Item Type:
Final Year Project
Identifiers:
Barcode : 00003095346
Accession Number : 875004525
Language:
English
Subject Keywords:
DDRII DRAM; technology development; algorithm
First presented to the public:
4/1/2009
Original Publication Date:
3/20/2018
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 91
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2018-09-19 12:01:10.033
Date Last Updated
2019-01-07 11:24:32.9118
Submitter:
Mohd Jasnizam Mohd Salleh

All Versions

Thumbnail Name Version Created Date
Drrii sdram stressing and validation algorithm (intel)1 2018-09-19 12:01:10.033