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Buffer Design for the Inductively-degenerated LNA for W-CDMA Application / Wong Pi Wei

Buffer Design for the Inductively-degenerated LNA for W-CDMA Application _Wong Pi Wei_E3_2009_875004503_00003095324_NI
Dalam tesis ini, satu reka bentuk penimbal CMOS bagi satu LNA PCSNIM WCDMA telah dicadang dan dianalisa dengan teliti. Penimbal ini adalah pengikut voltan kelas-AB mudah yang menggunakan satu kapasitor sebagai suap balik dan satu cermin arus kaskod sebagai litar pincangan. Bersama dengan PCSNIM LNA, reka bentuk penimbal ini telah disimulasi menggunakan Cadence SpectreRF. Reka bentuk ini telah dilaksana menggunakan teknologi Silterra 0.18μm dan menggunakan arus 0.99mA daripada 1.8V bekalan voltan. Penimbal ini beroperasi dengan PCSNIM LNA dalam julat frekuensi 2110MHz hingga 2170MHz. Di frekuensi 2.14GHz, S21 adalah 17.57dB, S12 adalah - 67.19dB manakala S11 dan S22 adalah masing-masing -16.41dB dan -24.45dB. NF adalah 1.82dB dan NFmin adalah 1.65dB. P1dB adalah -25.11dBm dan IIP3 adalah -14.56dBm. Berbanding dengan penimbal salur sepunya, penimbal ini mempunyai 16.65% keuntungan yang lebih rendah tetapi 16.69% kelinearan yang lebih tinggi. Selain daripada itu, ia menggunakan 37.34% arus yang lebih rendah. _________________________________________________________________________________________ In this thesis, a 0.18μm CMOS buffer design for a PCSNIM W-CDMA LNA was proposed and analyzed in detail. This buffer is a simple class-AB voltage follower which uses a capacitor as feedback and a cascode current mirror as the biasing circuitry. Together with the PCSNIM LNA, this buffer design was simulated using Cadence SpectreRF. This design was implemented using Silterra 0.18μm technology and draws 0.99mA current from the voltage supply of 1.8V. This buffer operates with the PCSNIM LNA in the frequency range of 2110MHz to 2170MHz. At frequency 2.14GHz, the S21 is 17.57dB, S12 is - 67.19dB while S11 and S22 are -16.41dB and -24.45dB respectively. The NF is 1.82dB and NFmin is 1.65dB. The P1dB is -25.11dBm and IIP3 is -14.56dBm. Comparing to common drain buffer, this buffer has 16.65% lower gain but 16.69% higher linearity. Besides of that, it consumes 37.34% lower current.
Contributor(s):
Wong Pi Wei - Author
Primary Item Type:
Final Year Project
Identifiers:
Accession Number : 875004503
Language:
English
Subject Keywords:
buffer design; biasing circuitry; capacitor
First presented to the public:
4/1/2009
Original Publication Date:
9/24/2018
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 102
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2018-09-24 16:00:20.51
Date Last Updated
2019-01-07 11:24:32.9118
Submitter:
Nor Hayati Ismail

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