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Building a clock for analog to digital converter timing test / Heng, Yeh En

Building a clock for analog to digital converter timing test_Heng Yeh En_E3_2010_875003004_00003079905_NI
Tesis tersebut bertujuan untuk menyediakan enam belas isyarat perangsang untuk menguji keberkesanan ADC. ADC yang perlu diuji mempunyai 40 pin. ADC tersebut berupaya untuk menukar analog input kepada dua belas digital output. Frekuensi isyarat-isyarat perangsang tersebut ditetapkan kepada 2 MHz dengan tahap voltan 3.3 V. Projek tersebut mengutamakan rekacipta litar yang murah and mudah. . Pendekatan yang dicadangkan untuk penyediaan isyarat-isyarat perangsang tersebut melibatkan penggunaan IC yang senang diperolehi daripada makmal universiti. Secara ringkasnya, litar yang diperkenalkan boleh dibahagikan kepada tiga bahagian yang penting; ring oscillator yang berfrekuensi 2MHz, liter untuk penyelenggaraan kitaran jam dan litar untuk penyelenggaraan tahap voltan jam. Model yang dibina atas PCB mempunyai prestasi yang lebih stabil jika dibandingkan dengan model yang dibina atas breadboard. Konsep rekacipta litar adalah disahkan melalui perisian MULTISIM sebelum dibina di atas breadboard atau PCB. Keputusan yang diingini telah diperolehi melalui eksperimen yang dijalankan. Konsep yang terlibat dalam rangkaian litar tersebut adalah tidak rumit dan mudah difahami. Selain daripada itu, satu eksperimen tentang pembilang (counter) juga dijalankan. Secara keseluruhannya, isyarat-isyarat perangsang yang dibina dalam projek ini merupakan antara cara-cara yang terbaik memandangkan ia membekalkan output yang lebih stabil dengan kejituan yang tinggi. _____________________________________________________________________________________ This thesis presents the building of a low-cost, high precision clock for the ADC timing test. There are sixteen clock stimuli required to drive the ADC chip. The 40-pin device-under-test (DUT) ADC is having a resolution as high as 12-bit. The frequency of the designed clock is 2 MHz and the voltage level is 3.3V. The proposed approach utilizes the use of simple digital logic gates to perform all the sixteen clock generation. In short, the circuit is divided into three parts; constant frequency ring oscillator, duty cycle adjustment circuit and voltage regulation circuit. Extra care is emphasized in selecting the most appropriate logic gates for circuit as different family and manufacturer of the gates leads to different results. In the proposed methodology, the model is built on a printed circuit board for a more stable performance. The test methodology was verified in simulation using MULTISIM as well as in hardware. Results show that the proposed methods in generating clocks are easy and accurate. The concept involved in the whole circuit is not complicated and easy to be comprehended. Besides, a 6-bit digital counter is constructed as the supplementary circuitry to test the digital-to-analog converter (DAC). The DAC is meant to translate back the digital output from the ADC to the analog output. Comparison between the DAC analog output and the original analog input is essential to verify the performance of the ADC. As a conclusion, the proposed clock design is the best options compared to others.
Contributor(s):
Heng, Yeh En - Author
Primary Item Type:
Final Year Project
Identifiers:
Accession Number : 875003004
Barcode : 00003079905
Language:
English
Subject Keywords:
sixteen clock stimuli required to drive the ADC chip; 40-pin device-under-test (DUT) ADC is having a resolution as high as 12-bit; constant frequency ring oscillator, duty cycle adjustment circuit and voltage regulation circuit.
First presented to the public:
4/1/2010
Original Publication Date:
3/19/2018
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 98
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2018-03-19 15:52:21.785
Date Last Updated
2019-01-07 11:24:32.9118
Submitter:
Nor Hayati Ismail

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Building a clock for analog to digital converter timing test / Heng, Yeh En1 2018-03-19 15:52:21.785