Dalam penerima frekuensi radio (RF), terdapat satu blok yang memainkan peranan penting iaitu penguat hingar rendah (LNA). Kini, banyak penyelidikan dan kajian telah dijalankan untuk meningkatkan prestasi LNA kerana begitu banyak cabaran untuk mengendali serta menghasilkan LNA yang berfungsi dengan bagus dari segi penggunaannya. Cabaran yang perlu diatasi adalah mengekalkan gandaan tinggi dan rata sepanjang jalur lebar yang diinginkan sementara mengekalkan kestabilan parameter lain seperti penggunaan kuasa, S-Parameter dan Noise Figure (NF). Dengan kemajuan teknologi serta saiz transistor yang semakin mengecil, cabaran menjadi semakin sukar kerana keperluan kuasa yang rendah. Projek ini berkaitan dengan penguat hingar rendah (LNA) tanpa pengaruh dengan menggunakan topologi perintang selari timbal-balik untuk aplikasi frekuensi sangat rendah (VLF) sehingga frekuensi sangat tinggi (VHF). 0.001 hingga 43MHz telah direka-bentuk menggunakan teknologi Silterra 0.13um CMOS. Litar ini disahkan melalui simulasi skematik menggunakan Cadence SpectreRF sepanjang frekuensi operasi. Gandaan yang diperolehi adalah 21dB mendatar dengan NF<5dB. Kuasa gandaan adalah 21 dB dengan kedua-dua refleksi masukan dan keluaran S11 dan S22 kurang daripada -10 dB. Pemencilan balikan S12 pula adalah < -40 dB, dan kesamaan metric adalah -10.02dBm untuk IP1 dB dan -1.62dBm. Keseluruhan LNA menggunakan 12.6mW kuasa pada 1.2V.
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Within any radio frequency (RF) receiver, consists one important block that plays a very significant role which is the Low Noise Amplifier (LNA). Up until now, many research and studies have been conducted to enhance the LNA’s performance as there are many challenges to handle in order to produce the LNA which works best for its application. The design challenges are to obtain a flat high gain across the desired bandwidth while balance with the other performance metrics such as power consumption, S-Parameter (SP) as well as Noise Figure (NF). With the advancement in technology and as transistor gets smaller, the challenge becomes more tensed due to the small power requirement. Besides the requirement for small power consumption, size of the circuit is also a very important aspect to be considered in integrated circuit (IC) design. This project is on the design of an inductor-less LNA using resistive shunt feedback topology for VLF to VHF applications. Resistive Shunt Feedback topology is used in this design because it provides good constant gain across the desired bandwidth with less area of fabrication. The 0.001 to 43 MHz LNA was designed using Silterra’s 0.13μm CMOS process. The circuit was verified through schematic simulation using Cadence Spectre RF over the covered band. The gain achieved is a flat 21dB with the noise figure (NF) < 5dB. The power gain, S21, is 21dB with both input and output reflection coefficients S11 and S22 are less than -10 dB. Reverse isolation is < -40 dB, and the linearity metrics are -10.02 dBm for IP1dB and -1.62 dBm for IIP3. The whole LNA consumes 12.6 mW of power at a VDD of 1.2 V.
Design of A 0.13μm CMOS LNA using resistive shunt feedback for 1 KHz to 43 MHz frequency application / Mior Abdul Azeem Mior Mustaffa Kamal