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Implementation of fpga based encryption chip using vhd - data encryption standard (des) algorithm /Lim Mui Liang

Implementation of fpga based encryption chip using vhd - data encryption standard (des) algorithm_Lim Mui Liang_E3_2006_NI
Inkripsi mempunyai sejarah yang menarik. Algoritma inkripsi tradisional adalah asas perisian kerana algoritma ini melibatkan operasi yang kompleks. Algoritma dengan asas perkakasan dapat direalisasikan dengan penggunaan FPGA. Terdapat banyak penyelidik menggunakan algoritma DES untuk diimplemenkan dalam FPGA. Tujuan projek ini adalah pengimplementasian cip inkripsi berasaskan FPGA dengan algoritma DES. Dalam projek ini, kesesuaian aplikasi algoritma DES dalam FPGA akan dikaji. Peringkat pertama projek ini ialah memahami aliran algoritma DES. Pada peringkat kedua, sistem ini dituliskan dalam kod VHDL. Pada peringkat ketiga, simulasi bagi kod VHDL dilakukan untuk tujuan pengesahan dengan menggunakan perisian ‘Altera Quartus II’. Keputusan menunjukkan algoritma DES boleh diimplementasi pada papan Altera UP2. Produk akhir projek ini adalah sebuah cip inkripsi DES yang berasaskan FPGA dan dapat inkrip atau dikrip 64-bit masukkan dengan 64-bit kunci. Cip inkripsi DES ini mempunyai rangkaian yang mudah, jitu, mempunyai kebolehgunaan yang tinggi dan cepat. Frekuensi maksima yang boleh digunakan oleh sistem ini ialah 29.33MHZ dan jumlah elemen logic yang digunakan hanya 708LE. ______________________________________________________________________________________ Cryptography has a long and fascinating history. Traditional Encryption Algorithms are implemented in software base because of the complexities involved in the operations. The hardware based of encryption chip become realizable with Field Programmable Gate Arrays (FPGAs). There are many researchers used Data Encryption Standard (DES) Algorithm to implement in FPGAs. The purpose of this project is to implement FPGA Base Encryption Chip using DES algorithm. Throughout the project, the suitability of the implementation DES algorithm in FPGA will be investigated. The first stage of this project is to understand the algorithm flow of the DES. In second stage, the system is described using Very High Speed Integrated Circuits hardware description language (VHDL). In third stage, compilation and simulation for source code verification purpose is done to yield the correct output by using Altera Quartus II 5.0 software. Result shows that DES algorithm can be implementing in Altera UP2 Board. The final product of this project is a FPGA DES Encryption Chip that is capable to encrypt or decrypt 64-bit blocks with 64-bit key. It has a simple architecture, high accuracy, high applicability and high speed. The maximum possible frequency can be used for the system is 29.33 MHz and the total of logic element used is only 708LE.
Contributor(s):
Lim Mui Liang - Author
Primary Item Type:
Final Year Project
Language:
English
Subject Keywords:
Cryptography; "secret writing”.; malicious hackers,
First presented to the public:
5/1/2006
Original Publication Date:
1/10/2019
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 121
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2019-01-10 15:58:10.821
Submitter:
Nor Hayati Ismail

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