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Preliminary phase noise studies of quadrature voltage control oscillator for 0.13mm cmos technology / Ng Kean Giap

Preliminary phase noise studies of quadrature voltage control oscillator for 0.13mm cmos technology_Ng Kean Giap_E3_2010_875003568_00003084258_NI

Abstract Menuju ke dekad kedua pada abad ke-21, teknologi perhubungan tanpa wayar dan litar frekuensi radio terus berkembang dengan pesat. Proses pengecilan-skala dalam teknologi telah menyebabkan rekabentuk litar RF menjadi lebih mencabar, terutamanya pangayun. Dalam projek ini, saya akan menunjukkan cara pendekatan teori tentang hingar fasa dalam LP3-QVCO dengan teknologi proses CMOS 0.13 mm. Litar ini dibina dengan 8-metal, 1-poly dan 1.2V sumber voltan. Frekuensinya ialah 5GHz. Rekabentuk tersebut memperbaiki prestasi malalui 40W perintang sumber (Rdamp), 200W perintang ekor (Rtail ) dan 50W penimbal keluaran. Litar tangkinya mengandungi induktor dalam-chip dan varaktor CMOS. Induktor delam-chip direkacipta dengan menggunakan "Analysis and Simulation of Spiral Inductance and Transformers" (ASITIC). Induktor tersebut mencapai faktor kualiti sebanyak 18.6 pada frekuensi tengah. Manakala varaktor CMOS tersebut merupakan multifinger gate width PMOS varaktor (3.125 m m  64 = 200 mm) dan ia boleh dilaras dari 0.2V sampai 1.2V. Pendekatan teori akan ditunjukkan dengan menggunakan Model Leeson. Dengan merujuk kepada litar tersebut, cara pengiraan analitik kepada setiap parameter akan ditunjukkan langkah demi langkah, terutamanya faktor kualiti (Q), angka hingar (F), dan kuasa keluaran (P). Seterusnya simulasi akan dijalankan untuk mengesahkkan pendekatan teori. Selain itu, keputusan proses pengukuran juga akan dibandingkan. _________________________________________________________________________________________ Toward the second decade of the 21st century, wireless communication technology and radio frequency circuit is keep developing. The aggressive progress in down-scaling of the technologies has caused the RF design to be more and more challenging, especially frequency synthesizer. This work will present the theoretical approach of phase noise on a 0.13 mm deepsubmicron CMOS process technology LP3-QVCO. This 8-metals, 1-poly, 1.2 V LP3-QVCO has a 5 GHz center frequency. This design improve output performance utilizing 40W source damping resistor (Rdamp), 200W tail biasing resistor (Rtail ) and 50W impedance common drain output buffers. The tank circuit consists of an on-chip spiral indctor and a CMOS varactor. The spiral inductor is designed using "Analysis and Simulation of Spiral Inductance and Transformers" (ASITIC). The inductor has a quality factor of 18.6 at the center frequency. The CMOS varactor is a multifinger gate width PMOS varactor (3.125 mm  64 = 200 mm) and it is tunable from 0.2 V to 1.2 V. The theoretical approach is carried out using Leeson model. Based on the model, some analytic calculations for each parameter will be presented step by step, especially the quality factor (Q), noise figure (F), and output carrier power (P). Then, simulation is performed to validate the theoretical approach. Furthermore, measurement result will be compared as well.

Contributor(s): Ng Kean Giap - Author Primary Item Type: Final Year Project Identifiers: Accession Number : 875003568 Language: English Subject Keywords: wireless communication technology; Spiral Inductance; multifinger gate First presented to the public: 4/1/2010 Original Publication Date: 7/31/2018 Previously Published By: Universiti Sains Malaysia Place Of Publication: School of Electrical & Electronic Engineering Citation: Extents: Number of Pages - 76 License Grantor / Date Granted:   / ( View License ) Date Deposited 2018-07-31 11:39:16.192 Date Last Updated 2019-01-07 11:24:32.9118 Submitter: Nor Hayati Ismail

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