Satu rekabentuk litar penguat beban fana teratur kembar (DRGC TIA) terperinci dan
bersistematik untuk sistem komunikasi cahaya kelihatan berjarak dekat dengan menggunakan
Cadence proses teknologi CMOS 0.18um telah diaplikasikan di dalam tesis ini. Pada masa ini,
kebanyakan sistem komunikasi wayarles adalah dijanakan daripada frekuensi radio (RF).
Peningkatan penggunaan sistem RF menyebabkan sistem itu mengalami beban berlebihan
seterusnya mengalami gangguan. Manakala infamerah mempunyai kadar penghantaran yang
rendah, justeru tidak sesuai digunakan dalam system komunikasi berkelajuan tinggi. Matlamat
utama kajian ini adalah untuk mengkaji gandaan dan lebar DRGC TIA dalam sistem komunikasi
berkelajuan tinggi. Dalam tesis ini, litar DRGC TIA dibahagi kepada tiga bahagian, antaranya
pemacu arus, penguat litar sepunya dan penguat beban fana teratur (RGC TIA). Setiap bahagian
direkabentuk secara berasingan dan kemudiannya digabungkan untuk menbentuk DRGC TIA.
Ini djalankan seriring analisis litar dan metodologi rekabentuk dalam Cadence Virtuoso
Schematic Editing dan Cadence Virtuoso Analog Design Environment. Keputusan pra bentangan
simulasi menunjukkan RGC TIA dapat mencapai kadar peningkatan 96.5 dan 1.81
jalur lebar manakala DRGC TIA mencapai 100.40 peningkatan dan 43.29 jalur
lebar. Keputusan simulasi menunjukkan DRGC TIA menpunyai kadar peningkatan dan jalur
lebar yang lebih baik berbanding dengan RGC TIA. Di samping itu, didapati bahawa keputusan
simulasi pasca bentangan and pra bentangan DRGC TIA adalah sama. Kesimpulannya, DRGC
TIA untuk sistem komunikasi cahaya kelihatan berjarak dekat telah berjaya direkabentuk.
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A detailed and systematic design of the Double Regulated Cascode (DRGC) transimpedance
(TIA) circuitry for short range visible light communication by utilizing Cadence 0.18
CMOS process technology is presented in this thesis. Most wireless communications today are
produced from radio frequency (RF). However, with the increasing usage of data, the RF system
becomes overload and uses up valuable and limited RF spectrum thus creates electromagnetic
interference. Whereas in infrared communication, the data transmission rate is slow therefore not
suitable to be used in high speed communication system. The main purpose of this research was
to investigate the gain and bandwidth of the DRGC TIA circuitry for high speed communication
system. In this thesis, DRGC TIA is divided into three parts including current mirror, common
drain amplifier and RGC TIA. Those parts were designed separately then they were combined
together to form a complete DRGC TIA circuitry. This is done by comprehensive circuit analysis
and design methodology in Cadence Virtuoso Schematic Editing and Cadence Virtuoso Analog
Design Environment. Simulations were conducted on RGC and DRGC TIA circuitry to
investigate their gain and bandwidth. Pre layout simulation results revealed that the RCG TIA
exhibits gain of 95.56 and 1.813 while the DRGC TIA circuitry exhibits gain of
100.40 and 43.29 bandwidth. From simulation results, DRGC TIA exhibits better
gain and bandwidth as compared to RGC TIA. In addition, the post layout simulation of DRGC
TIA was found to be same as the pre layout simulation. The principal conclusion was the CMOS
DRGC TIA circuitry for short range visible light communication was successfully designed.
Design and simulation of the transimpedance amplifier for short range visible light communication / Ooi Jia Loong