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Design of a high gain low noise amplifier for wideband code division multiple access (W-CDMA) aplications using silterra 0.18 mm / Mak Pui Fern

Design of a high gain low noise amplifier for wideband code division multiple access (W-CDMA) aplications using silterra 0.18 mm
This thesis presents a sub-mA, low-noise, high-gain CMOS low noise amplifier (LNA) for Wideband-Code Division Multiple Acess (W-CDMA) based on 0.18 μm CMOS technology. The LNA for W-CDMA which is covering a frequency range from 2110 MHz to 2171 MHz is the first gain element in the receiver architecture. It is designed for the direct conversion receiver (DCR). A few design techniques were studied. They were classical noise matching, simultaneous noise and input matching (SNIM), power constrained noise optimization (PCNO), and power-constraint simultaneous noise and input matching (PCSNIM). Low-noise under power-constrained can be achieved by using an inductive cascode degeneration amplifier with an extra gate-source capacitor. Gain enhancement can be obtained by using capacitive feedback at the cascode transistor. To verify the effectiveness of Cf, a numerical approach was done from simulation. From this approach, it is proven that by introducing a feedback capacitor Cf in this project, an increase of 6 dB is obtained compared to an LNA without Cf. This LNA consumes 3.795 mA of total current from a 1.8 V dc power supply. Impedance matching at the input and output is used to obtain good termination resistance (of 50Ω) in order to achieve good S11 and S22. The LNA was revised twice. Revision 0.0 is the initial design without any matching circuit. Revision 0.5 was obtained with impedance matching performed on the input and output. Next, Revision 1.0 was finalized after noise optimization was performed by reducing the shunt capacitance at the input matching circuit. Simulation results show a forward gain (S21) of 22.87 dB, input reflection coefficient (S11) of -12.6017 dB, output reflection coefficient (S22) of -12.4779 dB and reverse isolation coefficient (S12) of -29.2531 dB at the operating frequency of 2140 MHz. The low noise amplifier is able to provide a noise figure (NF) of 2.46 dB and a -13 dBm IIP3 at 2.14 GHz. The P1dB of the LNA is -26.8 dBm. The area of the fabricated chip is 1.5mm x 1.5mm. The overall performance of the LNA is able to conform to the specifications for a commercial LNA in W-CDMA systems. In order to simplify the calculations of the values of the components used in this project, two Matlab code are developed as well.
Contributor(s):
Mak, Pui Fern - Author
Primary Item Type:
Final Year Project
Identifiers:
Accession Number : 875002295
Language:
English
Subject Keywords:
Wideband-Code Division Multiple Acess; high-gain CMOS low noise amplifier ; power constrained noise optimization
First presented to the public:
1/1/2007
Original Publication Date:
10/4/2017
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 104
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2017-10-04 16:26:09.973
Date Last Updated
2019-01-07 11:24:32.9118
Submitter:
Nor Hayati Ismail

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Design of a high gain low noise amplifier for wideband code division multiple access (W-CDMA) aplications using silterra 0.18 mm / Mak Pui Fern1 2017-10-04 16:26:09.973