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Hardware Efficient Advanced Encryption Standard (AES) Co-Processor for Internet of Things (IoT) Devices

Hardware efficient advanced encryption standard (AES) co-processor for internet of things (IoT) devices / Ung Shen Jie
Penghantaran maklumat dengan selamat merupakan salah satu tugasan yang mencabar bagi merealisasikan Barang Dengan Internet (IoT). Penyulitan maklumat yang penting mesti dijalankan sebelum menghantar ke Internet. Antara kriptografi yang sedia ada, Piawai Penyulitan Lanjutan (AES) merupakan algoritma kriptografi yang paling banyak digunakan. Objektif projek ini adalah untuk mereka bentuk 128-bit AES pemproses keras yang mampu melaksanakan process menyulit, menyahsulit dan generasi kunci dengan mengunnakan Altera Cyclone V. Selain itu, AES yang direka perlu cekap dalam penggunaan sumber kerana sumber aldalah terhad dalam peranti IoT. AES yang direka juga harus sesuai untuk dilaksanakan dalam reka bentuk ASIC. Dalam kajian ini, 128-bit AES dilaksanakan dengan penggunaan sumber secara berkongsi, pengotimumman pusingan dalaman dan mengurangkan penggunaan memori. Reka bentuk akhir AES dalam kajian ini boleh mencapai penghasilan maksimum 1.636Gbit/s pada 148.24 MHz untuk kedua-dua proses penyulitan dan penyahsulitan. Reka bentuk akhir AES dibuktikan bahawa sumber dalam Altera Cyclone V FPGA mampu mencapai sekurang-kurangnya 2.5 kali lebih tinggi pemprosesan berbanding dengan kerja-kerja yang berkaitan. _______________________________________________________________________________________________________ Secure data transfer has been one of the most challenging task for Internet of Things (IoT) devices. Important data must be encrypted before ready to transfer. Among all of the cryptography measures, Advanced Encryption Standard (AES) is the most extensively used cryptographic algorithm in practice. The objective of this project is to design a synthesizable 128-bit AES hardware co-processor that is able to perform encryption, decryption and key generation on Altera Cyclone V FPGA. Besides, the designed AES has to be hardware efficient as resources are limited in IoT devices and is suitable to be implemented in ASIC design. This research implemented the 128-bit AES in ways such that resources are being shared, inner round pipelining optimization and minimize usage of registers or memory. Final design of AES in this research can achieve maximum throughput of 1.636 Gbit/s at 148.24 MHz for both encryption and decryption process. In this research, each of the logic element (LE) in FPGA can achieve at least 2.5 times more throughput compared to related work.
Contributor(s):
Ung Shen Jie - Author
Primary Item Type:
Final Year Project
Identifiers:
Accession Number : 875006069
Language:
English
Subject Keywords:
data transfer; challenging task; Internet of Things (IoT)
First presented to the public:
6/1/2016
Original Publication Date:
5/16/2018
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 96
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2018-06-20 10:29:08.623
Date Last Updated
2019-01-07 11:24:32.9118
Submitter:
Mohd Jasnizam Mohd Salleh

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Hardware Efficient Advanced Encryption Standard (AES) Co-Processor for Internet of Things (IoT) Devices1 2018-06-20 10:29:08.623