Dalamrekabentuk FPGA, saluranlaluanbertindaksebagaipenyambungantarakawasandalamandanluaran.Dengan
pertumbuhan get kiraan yang semakinpantassertarumitdalamproses nod28nm,
keperluanmasadaripadarekabentukiniadalahsukaruntukmencapaiperubahanuntuksem
ua PVT. Penganggaranmasa yang
terlebihbukansahajamenyebabkankegagalandalampencapaianmasamalahanmengakib
atkanpenampanyang tidakrealistikwujuddalamsaluranrekabentuk.
Laluanberkemungkinandinyatakandenganpelbagaikekanganmasaolehpemilik IP.
Laluanmasatidakakandianalisisdandioptimumkanapabilakekanganmasahilangdansa
mbungan yang tidaksahmunculdalamsaluranrekabentuk.Secaratidaklangsung,
inimengakibatkananalisisprestasimasatidakmencapaitahapyang dikehendaki.
Kewujudanpelanggaranmasa yang
banyakdalamsaluranrekabentukakanmemanjangkanmasapembangunanrekabentuk.
Masapengesahanalirandibangunkanuntukmengesahkanisuisumasapadaperingkatpermulaanrekabentukdanbertujuanuntukmenghasilkankeputus
anmasa yang lebihbagusdanseterusnyameningkatkanprestasimasa. LelaranECO
danusahapencapaianmasabolehdiperbaikidenganmelaksanakanaliranpengesahanmas
adanaliranpelanggaranmasasecaraautomatik.
Contohdigunakanujiankesuntukmenilaialiranpengesahanmasadanaliranpelanggaran
masasecaraautomatik. Denganmelaksanakanaliranpengesahanmasa,
keputusanmasabolehmeningkatsebanyak 65.26%
dalammemenuhipenyediaanmasadanpeningkatansebanyak 65.38% dalammemenuhipenahananmasa.Kesimpulannya, satuprosesberjayadihasilkanyang
mampumengenalpastiisu-isumasadanmeningkatkanprestasimasa.
TIMING PERFORMANCE ENHANCE FOR ROUTING CHANNEL IN 28NM FPGA CHIP
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In FPGA design, the routing channel acts as the access area for interconnect
in between the core and the periphery. With the rapid growth of gate counts and
complexity of routing channel design in 28nm process node, the timing requirement
of the design has difficulty to be met across entire PVT corner variations. Amongthe
timing closure issue occurs due to over-estimation of timing windows gets worse
and cause unrealistic guard-banding occurs in routing channel design. A path might
be also specified to multiple timing constraints by IP owners. The timing paths will
not be analyzed and optimized when the missing timing constraints and invalid
connection arisen in routing channel design. Consequently, the timing performance
analysisis not performed. Due to the complication mentioned, timing verification
flows are developed to verify the timing issues at initial design stage with the
intention to produce better timing results to enhance timing performance.ECO
iterationsand timing convergence effortsareimproved by timing verification flows
and automated fixing timing violations flow. The timing verification flows are
classified as missing timing verification flow, timing constraints conflict verification
flow, unrealistic timing constraints verification flow and stage delay calculator. A
design example is used as a test case to evaluate the timing verification flows and
automated fixing timing violations flow. Significant timing improvement is
observed in this test case. The timing results after timing verification flows shows
65.26% improvement on setup time closure and 65.38% improvement on hold time
closure. In conclusion, the timing verification flows and automated fixing flow are
successfully developed to identify the timing issues to improve timing performance.
Timing performance enhance for routing channel in 28nm fpga chip_Kin Si Kee_E3_2013_MYMY