Design of a 1.8v analog-to-digital converter (adc) delta-sigma modulator for integrated bluetooth applications using 0.18µm cmos technology / Ng Jiun How
Delta-sigma modulator is the most vital part of a converter that does the job of converting analog signal into a noise-shaped low-resolution digital signal. A 17-level, 2nd order ADC delta-sigma modulator with oversampling ratio of 32 when clocked at 32 MHz has been successfully designed and tape-out. The modulator is capable to achieve a worst case peak signal-to-noise-plus-distortion ratio (SNDR) of 70.6 dB and 74.43 dB of dynamic range over a 500 kHz bandwidth. The 1-mm2 modulator is physically implemented with Silterra 0.18 μm mixed-signal CMOS process and consumes only 5.3 mA of current from a 1.8 V supply. Correlated double sampling integrators have been used in this project to suppress the flicker noise in the CMOS implementation. Since the modulator employs a multi-bit architecture, a first-order mismatch noise-shaping encoder is used to shape the noise caused by device mismatches in the circuit.
Design of a 1.8v analog-to-digital converter (adc) delta-sigma modulator for integrated bluetooth applications using 0.18µm cmos technology / Ng Jiun How