| |
| The purpose of this book is to present computer arithmetic for fixed-point, decimal,
and floating-point number representations for the operations of addition, subtraction,
multiplication, and division, and to implement those operations using the Verilog
Hardware Description Language (HDL). The Verilog HDL language provides a
means to model a digital system at many levels of abstraction.
The four basic operations are implemented in the execution unit of a computer
which includes the arithmetic and logic unit (ALU). The execution unit is the focal
point of the computer and performs all of the arithmetic and logical operations.
Addition and subtraction for all three number representations are relatively simple;
however, multiplication and division are comparatively more complex. The
arithmetic algorithms for the three number representations are presented in sufficient
detail to permit ease of understanding.
The different modeling constructs supported by Verilog are described in detail.
Numerous examples are designed in each chapter for specific operations using the
appropriate number representation, including both combinational and clocked
sequential arithmetic circuits. Emphasis is placed on the detailed theory and design
of various arithmetic circuits using applicable algorithms. The Verilog HDL design
projects include the design module implemented using built-in primitives, dataflow
modeling, behavioral modeling or structural modeling, the test bench module, the
outputs obtained from the simulator, and the waveforms obtained from the simulator
that illustrate the complete functional operation of the design.
The book is intended to be tutorial, and as such, is comprehensive and self contained.
All designs are carried through to completion — nothing is left unfinished or
partially designed. Each chapter includes numerous problems of varying complexity
to be designed by the reader.
Chapter 1 covers the number systems of different radices, such as binary, octal,
binary-coded octal, decimal, binary-coded decimal, hexadecimal, and binary-coded
hexadecimal. The chapter also presents the number representations of sign magnitude,
diminished-radix complement, and radix complement.
Chapter 2 presents a review of logic design fundamentals, including Boolean
algebra and minimization techniques for switching functions. The minimization
techniques include algebraic minimization using Boolean algebra, Karnaugh maps,
map-entered variables, the Quine-McCluskey algorithm, and the Petrick algorithm.
Various combinational logic macro functions are also presented. These include multiplexers
of different sizes and types, such as linear-select multiplexers and nonlinear-
select multiplexers. The chapter also shows a one-to-one correspondence
between the data input numbers di of a multiplexer and the minterm locations in a
© 2010 by Taylor & Francis Group, LLC
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xvi Preface
Karnaugh map. Decoders and encoders are presented together with comparators.
Sequential logic includes SR latches, D flip-flops, and JK flip-flops. Counters of different
moduli are designed for both count-up and count-down counters. The complete
design process for Moore and Mealy synchronous sequential machines is
presented.
Chapter 3 introduces Verilog HDL, which will be used throughout the book to design
the arithmetic circuits. Verilog HDL is the state-of-the-art method for designing
digital and computer systems and is ideally suited to describe both combinational and
clocked sequential arithmetic circuits. Verilog provides a clear relationship between
the language syntax and the physical hardware. The Verilog simulator used in this
book is easy to learn and use, yet powerful enough for any application. It is a logic
simulator — called SILOS — developed by Silvaco International for use in the design
and verification of digital systems. The SILOS simulation environment is a method to
quickly prototype and debug any logic function. It is an intuitive environment that displays
every variable and port from a module to a logic gate. SILOS allows single-stepping
through the Verilog source code, as well as drag-and-drop ability from the source
code to a data analyzer for waveform generation and analysis. This chapter introduces
the reader to the different modeling techniques, including built-in primitives for logic
primitive gates and user-defined primitives for larger logic functions. The three main
modeling methods of dataflow modeling, behavioral modeling, and structural modeling
are introduced.
Chapter 4 presents fixed-point addition. The different categories of addition circuits
are: ripple-carry addition, carry lookahead addition, carry-save addition, memory-
based addition, carry-select addition, and serial addition. A ripple-carry adder is
not considered a high-speed adder, but requires less logic than a high-speed adder
using the carry lookahead technique. Using the carry lookahead method, a considerable
increase in speed can be realized by expressing the carry-out couti of any stage i as
a function of the two operand bits ai and bi and the carry-in cin–1 to the low-order
stage0 of the adder. Carry-save adders (CSAs) save the carry from propagating to the
next higher-order stage in an n-bit adder. They can be used to add multiple bits of the
same weight from multiple operands or to add multiple n-bit operands. With the
advent of high-density, high-speed memories, addition can be easily accomplished by
applying the augend and addend as address inputs to the memory — the outputs are the
sum. A carry-select adder is not as fast as the carry lookahead adder, however it has a
unique organization that is interesting. The carry-select principle produces two sums
that are generated simultaneously. One sum assumes that the carry-in to that group
was a 0; the other sum assumes that the carry-in was a 1. The predicted carry is
obtained using the carry lookahead technique which selects one of the two sums. If a
minimal amount of hardware is a prerequisite and speed is not essential, then a serial
adder may be utilized. A serial adder adds the augend and addend one bit per clock
pulse — thus, eight clock pulses are required to add two bytes of data. |
|
| Contributor(s): |
|
Cavanagh Joseph - Author |
| Primary Item Type: |
| E-book |
| Subject Keywords: |
| Verilog HDL; skipping over zeroes; $readmemb; endcase ; cout |
| Sponsor - Description: |
| Pusat Pengajian Kejuruteraan Elektrik & Elektronik - |
| First presented to the public: |
| 1/1/2010 |
| Original Publication Date: |
| 10/11/2017 |
| Previously Published By: |
| CRC Press, Taylor & Francis Group |
| Place Of Publication: |
| School of Electrical & Electronic Engineering |
| Citation: |
|
| License Grantor / Date Granted: |
|
/ ( View License )
|
| Date Deposited |
|
2017-11-10 16:39:00.594 |
| Date Last Updated |
|
2020-04-27 15:47:48.342 |
| Submitter: |
|
Mohd Fadli Abd. Rahman |
|
Computer Arithmetic and Verilog HDL Fundamentals