Keselamatan Litar Bersepadu(LB) merupakan isu besar kepada banyak syarikat korporat kerana banyak peranti tiruan telah wujud di pasaran. Banyak langkah keselamatan telah diambil untuk mengatasi masalah ini seperti litar keselamatan anti ceroboh(LKAC), litar cegah gangguan voltan dan penyulitan data. Kebanyakan LB hanya beroperasi pada satu frekuensi sahaja. Ini sangat merugikan kuasa apabila LB tidak membuat apa-apa operasi. Kajian ini bertujuan mereka LKAC yang mudah dan berkuasa rendah. Ia juga menguji beberapa frekuensi untuk mendapatkan jumlah kuasa yang rendah. Jumlah kuasa dibanding antara LKAC asal dan LKAC baru. LKAC baru menggunakan peranti logik yang optimum dan beroperasi pada frekuensi yang lebih rendah. Kuasa akan dikira menggunakan anggaran “spice”. Kajian berikutnya membandingkan jumlah kuasa yang digunakan oleh LKAC yang baru melalui Spice dan melalui perisian penganalisa kuasa seperti RedHawk. Tujuan kajian ini adalah untuk membuktikan penjimatan kuasa. Berdasarkan kedua kajian di atas, boleh dirumuskan bahawa pengurangan peranti logik dan kawalan frekuensi yang optimum boleh mengurangkan penggunaan kuasa sebanyak 96.6%. Nilai ini adalah satu anggaran yang pesimistik dan jumlah penjimatan adalah lebih tinggi sebenarnya. Jadi, keselamatan LB boleh dijaga dan jumlah kuasa boleh dijimatkan semasa LB tidak beroperasi.
Integrated Chip (IC) security has been a big concern for companies and consumers as the number of counterfeit devices have increased tremendously. Many counter-measures have been taken to improve the chip security like anti-tamper mesh, glitch protection and encryptions. The current anti tamper mesh usually runs on a single frequency and would consume a lot of power when the chip is idle. An inefficient mesh implementation would cause the die size to increase but the area protected would not be complete. This research will concentrate to make the anti-tamper mesh simple and secure yet, consumes low power. It uses the least resource in terms routing tracks and makes use of several operating frequencies to get the best of power consumption. The power number is compared using standard cell spice simulation numbers. The cells with reduced gate count and reduced frequency are compared with original settings using spice simulation number. The second experiment was done to compare the numbers from the spice simulations against power analysis tool. This is to ensure the spice simulation numbers reflect the power saving and to prove that the savings are real and can be even lower than estimated. Based on the experiments, it can be concluded that varying the frequencies of the active security mesh blocks and reduction of registers used can save power and still maintain the integrity of the active mesh. The spice simulation numbers are pessimistic and in power analysis, it is shown to be much lower. The total power saved by reducing the registers is 34.4%. When the registers and frequency are reduced, the total savings is about 96.6%.
Implementation of low power active security mesh Raj Kumar Krishnasamy