Dalam era komunikasi digital ini, peranti analog telah banyak digantikan dengan sistem digital disebabkan oleh kelajuan tinggi, kebolehpercayaan dan kosnya yang rendah berbanding dengan peranti analog. Oleh itu, Pemprosesan Isyarat Digital (DSP) telah menjadi topik penyelidikan popular yang terdiri dari pemprosesan isyarat ucapan dan pemprosesan imej. Dengan banyak penyelidikan yang berhasil sejak beberapa dekad yang lalu, pemprosesan isyarat digital telah beransur-ansur mengambil peranan penting dalam sistem komunikasi kerana tahap fleksibiliti yang tinggi. Walaupun mempunyai bentuk yang tidak teratur, fungsi asas ombak biasa digunakan kerana mereka mampu menguraikan isyarat kompleks kepada isyarat subband yang mempunyai lebar jalur yang terhad dan kemudian membina semula mereka dengan kehilangan sedikit maklumat. Ini bermaksud bahawa hanya terdapat sedikit kebocoran isyarat atau fasa peralihan daripada isyarat asal apabila isyarat direputkan. Secara kontras, penapis konvensional yang umum mempunyai masalah dengan kebocoran isyarat atau fasa peralihan yang perlu ditangani di output. Oleh itu, bank penapis FIR yang berdasarkan ombak direka dalam projek ini untuk melaksanakan penguraian dan pembinaan semula isyarat komposit. Projek ini terutamanya menumpukan pada reka bentuk dan pelaksanaan bank penapis FIR yang berdasarkan ombak di papan DSP TMS320VC35510 DSK. Objektif pertama projek ini dicapai di mana kajian tentang sistem bank penapis FIR berdasarkan ombak dijalankan dan pengetahuan tersebut digunakan dalam projek ini. Objektif kedua tercapai apabila bank penapis FIR berdasarkan ombak disimulasi dalam MATLAB dan hasilnya dianalisis. Setelah hasil daripada simulasi memuaskan, objektif ketiga iaitu untuk melaksanakan bank penapis tersebut dalam TMS320VC5510 DSP Starter Kit tercapai dengan membangunkan algoritma ‘decimation’ sehingga tahap 1 dalam Code Composer studio (CCS). Dari hasil simulasi tahap 1 interpolasi, pancang 0.8π, 0.7π, 0.5π, 0.3π, 0.2π dipulihkan dan reka bentuk bank penapis Daubechies 6 disahkan. Dari analisis output grafik DSK, kesimpulan dibuat bahawa bahagian ‘decimation’ daripada bank penapis yang sempurna yang selaras dengan teori berjaya direka. Walaupun terdapat sedikit perbezaan kerana perilaku penapis bukan-ideal dan ralat pengkuantuman apabila menggunakan pemproses tetap titik 16-bit, keputusan output keseluruhan dapat diterima.
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In this era of digital communication, analog devices are being extensively replaced by digital system owing to its high speed, high reliability and low cost. Thus, Digital Signal Processing (DSP) has been a hot research topic ranging from speech signal processing and image processing. With a lot of fruitful research over the past few decades, DSP has gradually taken up an important role in communication system due to its high degree of flexibility. Despite having irregular shape, wavelet basis functions are commonly used because they are capable of decomposing complex signal into subband signals of finite bandwidth and then reconstructing them with little loss of information. That being said there is only little signal leakage or phase-shifting of the original signal when the signal is decomposed. Conventional filters generally have problems with signal leakage or phase-shifting that have to be dealt with at the output. Hence, a wavelet based FIR filter bank is designed in this project to perform decomposition and reconstruction of a composite signal. The project concentrates on the design, realization and implementation of the wavelet based FIR filter bank in the DSP board TMS320VC35510 DSK. The first objective of the project is attained where study on wavelet based FIR filter bank system is conducted and the knowledge is applied in the project. The second objective of the project is to design a wavelet based filter bank consisting of an analysis filter bank and a synthesis filter bank in MATLAB, followed by extensive analysis of the resultant signal based on knowledge of DSP. Once the simulation result is satisfied, the third objective which is to implement the filter bank in TMS320VC5510 DSP Starter Kit is achieved by developing the decimation algorithm up to level 1 in Code Composer Studio (CCS). From simulation results of level 1 of interpolation, spikes of 0.8𝜋,0.7𝜋,0.5𝜋,0.3𝜋,0.2𝜋 are recovered as the input and a perfectly constructed Daubechies 6 filter bank design is verified. From analysis of graphical output of DSK, it is concluded that decimation part of a perfect reconstruction wavelet filter bank in line with theory is successfully designed. Although there are slight difference due to non-ideal behavior of filter and quantization error when using 16-bit fixed-point processor, overall output results are acceptable.
Design of wavelet based FIR filter bank using DSP board / Koay Teng Zhang