Glic adalah isu utama yang menghadkan prestasi keseluruhan penukar digital-ke-analog (DAC). Isu glic menjadi lebih penting sekarang kerana skala teknologi bergerak ke arah saiz yang lebih kecil. Skala teknologi yang kecil membolehkan proses volta rendah, dan oleh itu fenomena glic menjadi lebin penting kerana skala penuh voltan output DAC menjadi lebih rendah. Kerja ini membincangkan pemindahan reka bentuk 12-bit pseudo-pengamiran sumber-arus rentetan-perintang hibrid DAC daripada CMOS proses SilterraC13 0.13μm 1.8V ke CMOS Model Teknologi Ramalan (PTM) 45nm 1.1V, dan juga reka bentuk glitch bertambah baik versi DAC dinyatakan di atas. Simulasi telah dilakukan dengan menggunakan model kes nominal CMOS PTM 45nm 1.1V. 12-bit hibrid DAC dinyatakan di atas terdiri daripada skim perintang binari berwajaran dan termometer pengekodan dalam 8-LSB dan 4-MSB segmen masing-masing untuk mengoptimumkan prestasi. Reka bentuk DAC yang glic bertambah baik dicapai dengan menggabungkan Arus-terhad Pemandu Mengurangkan ayunan (SRD). Arus-terhad SRD digunakan untuk mengurangkan ayunan voltan isyarat kawalan pensuisan dalam suis arus, dan pepaku arus semasa pensuisan. Dengan cara ini, Arus-terhad SRD mengurangkan kesan jam galakan melalui nod pengeluaran, dan seterusnya mengurangkan tenaga glic. Hasilnya, kadar pensampelan 12-bit hibrid DAC tersebut ialah 100MHz. Penggunaan kuasa ialah 22.2156 mW manakala tenaga glic ialah 17.4122 pVs. Keputusan menunjukkan reka bentuk ini mencapai peningkatan 40.83 % dalam pengurangan tenaga glic berbanding dengan versi asal. Selain itu, Arus-terhad SRD juga mencapai peningkatan 19.48 % dalam pengurangan tenaga glic berbanding dengan SRD menggunakan CMOS PTM 45nm 1.1V. Kesimpulannya, kerja ini mencapai tenaga glic yang rendah dan penggunaan kuasa yang rendah.
_______________________________________________________________________________________________________
Glitches are the major issue that limits the overall performance of a digital-to-analogue converter (DAC). The glitch issue is more important now due to technology scaling moves towards smaller size. The small technology scaling introduces low voltage process, and hence the glitch phenomenon becomes more significant as the full scale output voltage of a DAC becomes lower. This work discusses the design transfer of a 12-bit pseudo-differential current-source resistor-string hybrid DAC from SilterraC13 0.13μm 1.8V CMOS process to Predictive Technology Model (PTM) 45nm 1.1V CMOS process, and the design of glitch improved version of the aforementioned DAC. The simulations were performed using nominal case models of PTM 45nm 1.1V CMOS process. The 12-bit hybrid DAC ultilises the architectures of binary-weighted resistor and thermometer coding in 8-LSB and 4-MSB segments respectively in order to optimize performance. The glitch improved DAC design is achieved by incorporating a Current-limited Swing Reduced Driver (SRD). The Current-limited SRD is used to reduce the voltage swing of the switching control signal of current switches, and the current spikes during switching instants. By doing this, the Current-limited SRD minimizes the clock feed-through effect to the output nodes, and hence reduce the glitch energy. The simulation results show that the 12-bit hybrid DAC performed at a low power supply of 1.1 V with sampling rate of 100 MHz. The power consumption during full-scale current was 22.2156 mW. The glitch energy was 17.4122 pVs. The results show that this design achieves a 40.83 % improvement in glitch energy reduction as compared with the original version of DAC. Apart from that, the version of DAC with Current-limiter SRD also achieves a 19.48 % improvement in glitch energy reduction as compared with the version of DAC with SRD circuit. Overall, this work achieves a low glitch energy and low power consumption.
A 12-bit pseudo-differential current-source resistor-string hybrid digital-to-analogue converter with current-limited swing reduced driver / Ch’ng Heng Chiat