Nyahcas elektrostatik (ESD) merupakan faktor utama kepada kegagalan dan kerosakan
radio komunikasi dua hala. Kegagalan ralat anjal seperti kegagalan logik, selak-atas atau
tersalah set boleh berlaku disebabkan ESD secara berlebihan. Secara umumnya diketahui
bahawa peranti-peranti Semikonduktor Pelengkap Oksida-Logam (CMOS) amat terdedah
kepada ESD. Kegagalan CMOS yang disebabkan oleh ESD boleh juga menyebabkan radio
dua hala ditetapkan semula atau berhenti berfungsi sepenuhnya. Lazimnya, kegagalan ini
hanya boleh diketahui selepas radio dipasang and diuji. Melalui kajian ini, satu kaedah baru
telah dicipta untuk menguji risiko ESD pada peringkat litar radio. Vektor Poynting
digunapakai untuk mengira kuasa yang diterima oleh litar bersepadu semasa berlakunya ESD.
Melalui kaedah ini, radio dua hala telah dimodel secara 3-dimensi menggunakan piawaian
IEC 61000-4-2. Model ini dapat memberikan satu gambaran mengenai penyebaran arus ESD
di dalam Papan Litar Tercetak (PCB) dan satah bumi. Kuasa purata berpemberat masa (Stwa)
yang dikira melalui produk silang di antara medan-E dan medan-H diguna secara meluas
dalam permodelan, hasilnya nilai had maksimum sebanyak 3.7 W=m2 telah ditetapkan untuk
meramal kegagalan ESD. Keputusan simulasi komputer menunjukkan persetujuan yang baik
dengan nilai yang telah diukur di dalam had toleransi. Kajian ini mendapati bahawa radio
yang diperbaharui menggunakan batang logam mempunyai Stwa kurang dari had maksimum
berbanding radio asal. Kajian ini juga meramal kegagalan ESD akan berlaku pada 8 kV and
11 kV bagi radio asal dan diperbaharui masing-masingnya. Hasil kajian ini juga menghasilkan
satu skim baru bagi jurutera untuk menilai risiko ESD pada radio dua hala di peringkat PCB.
Mengenalpasti komponen yang paling berisiko kepada ESD di peringkat awal juga bermakna
kegagalan ESD dapat ditangani secukupnya sebelum pengeluaran secara besar-besaran.
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Electrostatic discharge (ESD) is a major cause of failures and malfunctions in two-way
communication radio. Soft error failures like logic error, latch-up and wrong reset can occur
as a result of the excessive ESD. It is a well-known fact that the Complementary Metal-Oxide-
Semiconductor (CMOS) devices are more susceptible to ESD. The failure of CMOS ICs due to
ESD can also cause radio to reset or shutdown completely. Presently the failures are detected
after the radio is built and tested only. In this research, new methodology is developed to assess
the ESD risk of two-way radio at circuit level. Poynting vector is used to calculate the incident
power received by susceptible integrated circuit during ESD. In doing so the two-way radio
is modeled in 3-D using the IEC 61000-4-2 standard. The result provides a graphical means
to visualize the propagation of ESD current in Printed Circuit Board (PCB) and ground plane.
Time-weighted average power density (Stwa) calculated as a cross product between E-field and
H-field was used extensively in the modeling, from which a maximum limit of 3.7 W=m2,
Stwa was established for predicting ESD failures. It was observed that results obtained through
computer simulation agree well with measured values within some tolerance limit. It was also
discovered that the improved radio with metal bar is well above this limit compared to the
original radio. It is also predicted that the soft error due to ESD would occur at 11 kV and 8
kV for improved and original radio respectively. Results from this study provide a new scheme
for engineers to assess ESD risk of two-way radio at PCB level. Identifying most susceptible
component to ESD allows radio failures to be addressed adequately before mass production.
Prediction of electrostatic discharge soft error on two-way radio using simulation and immunity scanning technique_Rosnah Antong_E3_2017_MYMY