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DD ENV 50218:1996 - Description of a parametrized European mini test chip

Description Printed version of this is available at library. To request, please e-mail to referencepk@usm.my and include a copy of this record in your e-mail. Abstract This publication documents the parameterized MOS test structures of the device model Parameter extraction Test Chip (PTC) of the European Mini Test Chip (ETC). The devices of the PTC are a subset of the devices of the ETC. The modules of the ETC provide a minimum set of test structures used to characterize a MOS technology. The test structures of the ETC are generated automatically by a computer program for a given MOS technology. The program also generates test structures which are designed to characterize reliability aspects of a MOS technology (Reliability Test Chip. RTC) [6, 7, 8].

Contributor(s): NAAR - Data Entry Person Primary Item Type: British Standard Identifiers: ICS 35.240 ISBN 0580261794 ICS 31.2000 Language: English Subject Keywords: Description; Parametrized European mini test chip First presented to the public: 2/2/2024 Original Publication Date: 9/15/1996 Previously Published By: British Standards Institution Place Of Publication: London, United Kingdom Citation: Extents: Number of Pages - 20 License Grantor / Date Granted:   / ( View License ) Date Deposited 2024-02-02 11:01:36.35 Submitter: Nurul Aini Abdul Rahman

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