aving is the process that randomizes the sequence of bit so that the burst of error is spread over multiple code-words. It seems like converting the long run burst of error into a random error that can be corrected easily by error correction codes. The interleaving system is use in improve the RFID (Radio Frequency Identification)’s transmission channel’s quality. HDL-based design flow is applied to develop the interleaving system. RTL coding development, gate level synthesis and automatic place & route are the three major stages in HDL-based design flow. Block diagram is developed in order to construct the RTL code in Verilog. Functional verification is performed before gate level synthesis. In synthesis step, RTL code is transform into gate level netlist. With the gate level netlist and testbench, gate level functional verification is performed to verify the functionality. Final step is translated the gate level netlist into layout and perform the post layout verification. The design is implemented with the Silterra 0.18 μm standard cell library. (16, 16) convolutional interleaving system consists of an interleaver at the transmitter side and a de-interleaver at the receiver side. The interleaver randomizes the sequence of bit and de-interleaver rearranges the interleaved data to the original data. For the interleaver core, the synthesized design consists of 598 cells and total dynamic power consumption is 5.16 mW. Meanwhile, de-interleaver core consists of 633 cells and total dynamic power consumption is 4.39 mW. The system developed in the project manages to reconstruct the interleaved data into the original data after 244 clock cycles. Theoretical, the time delay is 240 clock cycles, that is (N-1)B or 15x16 in this case. Another 4 clock cycles are introduced by the pipelining latency, 2 clock cycles for each interleaver and de-interleaver. In the post layout simulation, the clock to output delay is 5 ns. Post route slack times for interleaver are 0.039 ns for hold time and 3.492 ns for setup time. For de-interleaver, setup slack time is 3.409 ns and hold slack time is 0.090 ns. The slack time is positive, this show that the design have enough headroom for setup and hold time. Overall, the design performed well under 50 MHz clock’s frequency.
RFID DIGITAL BLOCK DEVELOPMENT INTERLEAVER DE-INTERLEAVER_Bong Pai Ho_E3_2007_875000148_NI