A fourth order bandpass filter with a center frequency of 40 MHz and bandwidth of 1.25 MHz is designed using CMOS 0.18 μm technology. In this thesis, the power consumption, linearity and noise performance of a CMOS Gm-C bandpass filter are studied. Two 40 MHz bandpass filters are designed and analyzed. Both filters are 4th-order bandpass filters constructed by cascading 2 stages of biquads. The first design of the filter uses only transconductance cells together with capacitors and resistors. The measured IIP3 of the first design is -3.45 dBm with a gain of 42.79 dB and the noise figure is 25 dB. The power consumption is 3.2 mW with a 1.8 V voltage supply. The resistance value reaches as high as 216 kΩ. It can be tuned from 8.38 MHz to 84.3 MHz. The second design of the filter employs negative transconductance cells together with transconductance cells, capacitors and resistors. The measured IIP3 of the second design is -4.33 dBm with a gain of 35.16 dB and the noise figure is 29 dB. The power consumption is 5.84 mW with a 1.8 V voltage supply. The second design which employs negative transconductance cells has reduced the resistance value to just a few kΩ without much effect on the performance of the filter. The tuning range of the second filter is from 8.38 MHz to 76.31 MHz.
Design of bandpass filter front-end receiver for cdma application at 900mhz using cmos technology_Ching Kai Lun_E3_2007_NI