Pada masa kini, kemajuan alat elektonik mudah alih seperti telefon pintar, jam pintar dan penyukat suhu digital telah membawa kepada inovasi dalam teknik rekabentuk kuasa rendah. Selain itu, pengecilan skala proses teknologi CMOS telah meningkatkan kepadatan transistor dalam sesuatu peranti. Hasilnya, peranti tersebut mempunyai banyak fungsi tetapi lebih banyak kuasa yang digunakan oleh satu unit kawasan. Kemudian, teknik pengurangan kuasa telah diterokai dalam rekabentuk litar sepadu elektronik. Dalam projek ini, teknik rekabentuk kuasa rendah telah dikaji untuk pembanding bagi penukar analog kepada digital kerana ia menggunakan kuasa yang banyak. Kajian ini adalah untuk menyiasat kebolehlaksanaan teknik kuasa rendah yang sedia ada untuk dilaksanakan dalam litar analog terutamanya pembanding. Teknik pengurangan kuasa seperti teknik transistor “sleepy”, teknik memutuskan CMOS (SCCMOS), teknik pengurangan VDD dan histerisis telah dikaji. Kemudian, prestasi pembanding Litar Rujukan, pembanding dengan pengurangan VDD dan pembanding dengan histerisis telah dibandingkan. Rekabentuk ini disimulasikan di dalam proses teknologi CMOS 0.13μm dengan persekitaran Cadence daripada Silterra. Daripada kajian ini, ia menunjukkan prestasi penggunaan kuasa adalah bertukar ganti dengan kelajuan pembanding. Histerisis yang digunakan dalam pembanding Litar Cadangan 3 menghasilkan prestasi yang baik dibandingkan dengan Litar Rujukan.daripada simulasi pra-rangka lantai, peratusan pengurangan kuasa statik dan dinamik bagi Litar Cadangan 3 masing-masing menunjukkan 77.18% dan 74.24%. Manakala lengah perambatan bagi Litar Cadangan 3 meningkat 27.78% berbanding Litar Rujukan. Walaupun lengah perambatan meningkat, kelajuan pembanding Litar Cadangan 3 masih dalam julat pembanding berkelajuan tinggi. Dalam simulasi pasca-rangka lantai, Pembanding Litar Cadangan 3 menunjukkan ciri-ciri statik seperti voltan ofset bernilai 12.9 mV, voltan gandaan 45.45 dan resolusi 26.4 mV. Perbezaan dalam peratusan antara simulasi pra-rangka lantai dan simulasi pasca-rangka lantai menunjukkan voltan ofset benilai 3.2%, voltan gandaaan 0.39% dan resolusi 0.38%. Kemudian, ciri-ciri dinamik menunjukkan lengah perambatan 0.59 ns dan frekuensi 1.69 GHz. Selain itu, penggunaan kuasa statik dan kuasa dinamik masing- masing menunjukkan 17.42 μW dan 23.11 μW. Simulasi pra-rangka lantai dan simulasi pasca-rangka lantai menunjukkan tiada kesan parasitic yang ketara terhadap prestasi pembanding Litar Cadangan 3.
_______________________________________________________________________________________________________
Nowadays, development of portable electronic device such as smartphone, smartwatch and digital thermometer has led to innovation of low power design technique. Besides that, scaling down of CMOS process technology has increased the transistor density. As a result, the device has higher functionality but more power is consumed per unit area. Then, power reduction technique is being explored in electronic integrated circuit design. In this project, low power design techniques are studied for Analog to Digital Converter (ADC) comparator because it consumes the most power. The study is to investigate the feasibility of the available low power techniques to be implemented in the analog circuit specifically for comparator. Power reduction techniques such as sleepy transistor technique, super cut-off CMOS (SCCMOS), reduced VDD technique and hysteresis was studied. Then, the performance of Reference Circuit comparator, reduced VDD comparator and comparator with Hysteresis was compared. The design is simulated in 0.13μm CMOS technology with Cadence environment from Silterra. From the study, it is shown that the performance of power consumption is trade-off with the speed of comparator. Hysteresis applied in Proposed Circuit 3 comparator result in good performance compared to Reference Circuit. From pre-layout simulation, percentage of static and dynamic power reduction of the Proposed Circuit 3 were 77.18% and 74.24% respectively. While, the propagation delay of the Proposed Circuit 3 was increased 27.78% from the Reference Circuit. Eventhough the propagation delay was increased, the speed of Proposed Circuit 3 comparator is within the range of high speed comparator. In post-layout simulation, Proposed Circuit 3 comparator shows static characteristics of offset voltage of 12.9 mV, voltage gain of 45.45 and resolution of 26.4 mV respectively. The difference in term of percentage between pre-layout and post simulation shows offset voltage of 3.2%, voltage gain of 0.39% and resolution of 0.38% respectively. Then, dynamic characteristic shows propagation delay of 0.59 ns and frequency of 1.69 GHz. Besides that, static power consumption and dynamic power consumption shows 17.42 μW and 23.11 μW respectively. The pre-layout simulation and post-layout simulation show there is no significant parasitic effect on the performance of the Proposed Circuit 3 comparator.
A study of high speed and low power design technique of comparator in analog to digital converter / Mohd Taufiq Efrizal