Satu kajian hingar yang terperinci dan sistematik untuk penguat hingar rendah (LNA) induktif
ternyahjana kaskod, yang juga dikenali sebagai topologi Padanan Masukan dan Hingar
Serentak (SNIM) LNA dipersembahkan dalam tesis ini. Senibina SNIM LNA akan dikaji dahulu.
Ini diikuti oleh kajian ke atas model hingar MOSFET standard dan khusus, di mana sumbangan
hingar daripada transistor kaskod (konfigurasi sama-gerbang) dipertimbangkan. Seterusnya,
model hingar MOSFET khusus digunakan untuk membangunkan teknik pengoptimuman hingar
dengan kekangan kuasa (PCNO) untuk pemilihan lebar optimum peranti. Kontur angka hingar
(NF) dibina sebagai kaedah grafik untuk memahami hubungan antara parameter rekabentuk (r,
Qs, and PD) dan juga untuk anggaran angka hingar bagi LNA. Tiga LNA direka menggunakan
metodologi rekabentuk Padanan Masukan dan Hingar Serentak dengan Kekangan Kuasa (PCSNIM).
Dua daripada PCSNIM LNA ini mempunyai frekuensi operasi 2.4 GHz, bekalan voltan
sebesar 1.8 V, dan direka menggunakan proses teknologi 0.18 mm daripada Silterra. PCSNIM
LNA ketiga direka menggunakan proses teknologi 0.13 mm daripada Silterra dengan bekalan
voltan 1.2 V dan frekuensi operasi 2.4 GHz. Kesemua LNA mempunyai penimbal keluaran bagi
50 W padanan keluaran, dua daripadanya (0.18 mm and 0.13 mm) mempunyai penimbal konfigurasi
sama-alir (CD) manakala satu lagi mempunyai penimbal kelas AB (0.18 mm). Seterusnya,
keputusan eksperimen diperolehi melalui simulasi. Metrik perlakuan yang diperolehi termasuk
S-parameter, angka hingar, linearitas (IP1dB and IIP3), dan perlakuan DC. Pecahan komposisi
angka hingar dilakukan untuk mengenal pasti sumbangan hingar untuk setiap komponen. Perbandingan
angka hingar yang diperolehi melalui perhitungan dan simulasi dijalankan seterusnya.
Didapati bahawa kontur angka hingar dan sebutan NF berdasarkan model hingar standard
menghasilkan keputusan yang memuaskan bila dibandingkan dengan keputusan simulasi.
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A detailed and systematic noise study of the inductively-degenerated cascode LNA, which
is also known as the Simultaneously Noise and Input Matching (SNIM) LNA is presented in this
thesis. The architecture of SNIM LNA is first studied. This is followed by studies on the standard
and extended MOSFET noise models, where noise contribution of the cascode(common-gate)
transistor is taken into consideration. Next, the extended MOSFET noise model is used to develop
the power-constrained noise optimization (PCNO) technique for the selection of optimum
device width. Noise figure contours are constructed as a graphical means to understand the relationship
of design parameters (r, Qs, and PD) and to estimate the noise figure of the LNA. Three
LNAs are designed using power-constrained simultaneous noise and input matching (PCSNIM)
design methodology. Two of these PCSNIM LNAs have the operating frequency of 2.4 GHz,
supply voltage of 1.8 V, and is realized using Silterra’s 0.18 mm process technology. The third
PCSNIM LNA is designed using Silterra’s 0.13 mm process technology with 1.2 V supply voltage
and 2.4 GHz operating frequency. All there LNAs have buffer for 50 W output matching, two of
which(0.18 mm and 0.13 mm) with common-drain buffer and the other with class AB buffer (0.18
mm). Subsequently, experimental results are obtained through simulation. The performance metrics
of interest include the scattering parameters, noise figure, linearity (IP1dB and IIP3), and DC
response. Noise figure breakdown for the LNA is performed to identify noise contribution for each
component. Comparison on noise figures obtained from calculation and simulation is then made.
It was found that the noise figure contour and NF expression based on the standard noise model
yield satisfactory result when compared to the simulation result.
MOSFET noise models, where noise contribution of the cascode(common-gate) transistor is taken into consideration; design parameters (r, Qs, and PD) and to estimate the noise figure of the LNA; PCSNIM LNA is designed using Silterra’s 0.13 mm process technology with 1.2 V supply voltageand 2.4 GHz operating frequency.
Preliminary noise study of low noise amplifier for 0.13 mm and 0.18 mm cmos process technologies_Koh Hee Lee_E3_2010_875003593_00003084285_NI