(For USM Staff/Student Only)

EngLib USM > Ω School of Electrical & Electronic Engineering >

A 1.8v 10-bit 100mss fully differential pipelined adc in cmos 0.18um process technology / Khoo Boon Hee

A 1.8v 10-bit 100mss fully differential pipelined adc in cmos 0.18um process technology / Khoo Boon Hee
Piawai Bluetooth™ merupakan salah satu penggerak utama bagi perhubungan tanpa wayar berjarak pendek. Kandungan Piawai Bluetooth™ adalah dari frekuensi 500Khz ke 25Mhz. Untuk pensampelan frekuensi serendah 3 Mhz ke bawah, rekaan ADC berciri SAR dan Delta-Sigma adalah pilihan utama manakala rekaan ADC berciri saluran paip adalah lebih sesuai untuk pensampelan frekuensi 5 mhz ke atas Matlamat penyelidkan ini adalah untuk memghasilkan rekaan ADC berciri saluran paip yang boleh digunakan untuk piawai Bluetooth™ dari BT1.1 sehingga BT4.0 dengan kuasa pensampelan sehingga 100MS/s dan 10 bit resolusi dengan bekalan kuasa 1.8V di bawah proses teknologi CMOS 0.18um dari Silterra. Operasi penguat berciri Flipped Voltage Follower (FVF) telah disyorkan untuk mencapai kuasa pensampelan yang tinggi. Rekaan ADC berciri saluran paip yang mengandungi 10 paip telah direka dan diuji di bawah pensampelan 50MS/s and 100MS/s. Pensampelan setinggi 50MS/s telah dicapai dengan penggunaan kuasa serendah 54mw. Peningkatan kuasa pensampelan boleh dicapai jika kuasa lebar jalur penguat di pertingkatkan melalui ciri penentukuran digital and litar suapbalik mod biasa. The Bluetooth™ standards is one of the major driving forces of the short-range wireless communications market as well as home and office environments. There are many Bluetooth™ standards covering the signal bandwidth from 500 khz to 25 mhz. For low frequency data sampling, SAR and Delta-Sigma ADC are preferred architecture for signal bandwidth of below 3 mhz and pipelined ADC is prefer for 5 mhz and above. This research is to deploy pipelined ADC as single architecture that able to cover Bluetooth™ standard from BT1.1 to BT4.0. The targeted sampling rate is 100MS/s with 10 bit resolution at 1.8V power and designed using Silterra CMOS 0.18um process. Flipped Voltage Follower (FVF) operational amplifier has been recommended as operational amplifier to achieve high sampling rate .Ten stages pipelined ADC was developed and tested at 50MS/s and 100MS/s. The sampling rate has achieved by measureable of 50MS/s and the power consumption is 54mw. Sampling rate can be increased further by improving the gain bandwidth of the FVF Op-Amp through the implementation of the digital calibration and common mode feedback (CMFB)
Contributor(s):
Khoo, Boon Hee - Author
Primary Item Type:
Thesis
Language:
English
Subject Keywords:
Analog; digital Converter; microcontroller; vmin and vmax; NMOS amplifier
Sponsor - Description:
Pusat Pengajian Kejuruteraan Elektrik & Elektronik -
First presented to the public:
1/1/2017
Original Publication Date:
3/9/2018
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 128
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2018-03-09 16:45:51.71
Date Last Updated
2020-05-28 18:10:24.511
Submitter:
Mohd Fadli Abd. Rahman

All Versions

Thumbnail Name Version Created Date
A 1.8v 10-bit 100mss fully differential pipelined adc in cmos 0.18um process technology / Khoo Boon Hee1 2018-03-09 16:45:51.71
Engineering Library USM @ 2017