Tesis ini bertujuan untuk membina satu pendaftar masuk selari, keluar siri bagi menguji keluaran daripada litar penukar analog ke digital (ADC). Pendaftar tersebut akan dipasang selepas ADC untuk membaca data 12-bit keluarannya. ADC ini mengandungi 40 pin dan dari 40 pin tersebut, 12 pin merupakan pin keluaran data. Pendaftar masuk selari, keluar siri dihasilkan dari satu susunan flip-flop dan get logik. Untuk menyenangkan pemahaman pembaca mengenai rekaan ini, kelengkapan operasi pendaftar boleh dibahagikan kepada tiga bahagian; pemilihan saiz data kemasukan, proses memasukkan setiap bit ke dalam flip-flop untuk disimpan dan anjak keluar setiap bit secara sesiri mengikut setiap denyut klok (clock). Untuk membina pendaftar bagi projek tersebut, penentuan penggunaan IC merupakan satu pertimbangan yang perlu diambil kira. Kepelbagaian jenis IC memberi keputusan yang berbeza berdasarkan ciri-ciri keluarga logik digital tersebut. Kebenaran seluruh rekacipta adalah disahkan melalui perisian MULTISIM dan seterusnya diuji di atas breadboard atau papan litar bercetak. Pendaftar masuk selari, keluar siri berupaya beroperasi pada frekuensi 2MHz dan mempunyai voltan keluaran sebanyak 3.3V.
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This thesis is about the design of a parallel to serial conversion circuitry for ADC output testing. Parallel to serial shift register is the subcircuit of the device which is placed after an analog to digital converter (ADC). The 40-pin device under test (DUT) has resolution as high as 12-bit. This 12-bit data will be the input into the designed circuit and as a result, a serial output is obtained at the output terminal. The parallel to serial shift register constructs of simple digital logic gates which were provided by the university’s laboratory. For simpler understanding, the operation of the circuit can be divided into three parts; selection of data bit length, loading data into the storage device and shifting out the data bit by bit to the output terminal. There are several logic families with different type of circuitry which may lead to different results. Therefore, this is one of the considerations given attention before going further into the details of the design. The simulation of the schematic design was verified using MULTISIM and experimented on breadboard for hardware implementation. In the proposed methodology, the circuit is built on a printed circuit board for a more stable perfomance. The designed parallel to serial shift register operates at the frequency of 2MHz and the output voltage is 3.3V. This design is able to load and shift data of length 8-bit, 10-bit and 12-bit.
Parallel to serial circuitry on printed circuit board_Alice Kho Ai Li_E3_2011_875004015_00003089571_NI