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Test circuit for adc ic testing / Khadijah Binti Hasbullah

Test circuit for adc ic testing_Khadijah Binti Hasbullah_E3_2010_875003595_00003084287_NI
Litar penguji yang direka bentuk untuk projek ini merangkumi litar bekalan kuasa, litar pincangan arus terus, litar jam dan juga litar pengesan keluaran digital yang digunakan untuk menguji ciri litar bersepadu ADC. Laporan ini mengandungi teori, pernyataan masaalah, penyelesaian kepada masaalah, langkah-langkah pengujian, keputusan serta rumusan berkaitan projek yang dibuat. Secara spesifik, projek ini memfokus kepada mereka bentuk dan membina litar penguji untuk mengenalpasti ciri statik litar bersepadu ADC 40 pin yang baru direkabentuk. Litar penguji dibina untuk menyediakan penyelesaian yang lebih murah untuk menguji IC. Bekalan voltan bernilai 3.3V diperlukan untuk memastikan ADC IC beroperasi. Voltan pincangan yang mempunyai empat nilai voltan yang berbeza juga diperlukan untuk proses pengujian. Voltan tersebut yang digunakan untuk memincang transistor dalam ADC (yang diwakili oleh BIAS1, BIAS2, BIAS3, BIAS4 and BIAS) disediakan oleh blok pincangan voltan arus terus yang direkabentuk bersama litar penguji ini. Selain untuk tujuan pincangan transistor, litar pincangan ini juga turut menyediakan voltan rujukan 1.2V kepada pin 𝑉𝑅𝐸𝐹 dan 𝑉𝐢𝑀 . Rekabentuk untuk kedua-dua litar iaitu litar bekalan kuasa dan litar pincangan arus terus mesti dibuat dengan teliti untuk mengelakkan sebarang gangguan baru dan menyediakan voltan rendah hingar yang sangat diperlukan bagi kejayaan pengujian ADC. Litar jam luaran yang disambung ke 16 pin ADC yang lain juga diperlukan bagi menyediakan denyut untuk pengujian ADC. Akhir sekali proses pengujian ADC menghendaki pelbagai nilai voltan dimasukkan ke pin 𝑉𝐼𝑁+ dan π‘‰πΌπ‘βˆ’ ADC tersebut. Keluaran digital proses pengujian dipertunjukkan oleh osiloskop digit. _____________________________________________________________________________________ A test circuit designed in this project consists of power supply circuit, dc biasing circuit, clock circuit and digital oscilloscope to test the characteristic of an ADC IC. A theory, problem statement, solution to the problem, procedures of testing, result and conclusion for the project are included in this report. Specifically the project focused on the designing and building of a test circuit to define the static characteristics of the newly designed 40 pins pipelined ADC IC. The test circuit is designed to provide a cheaper solution to test the IC. A dc voltage supply of 3.3V is required to power up the ADC IC (𝑉𝐷𝐷 pin). The biasing voltage of five different values is also necessary for the testing of the IC. These voltages are used to bias the transistors in the ADC IC (represented by BIAS1, BIAS2, BIAS3, BIAS4 and BIAS 5) are provided by the dc biasing block also designed together with this test circuit. Other then biasing the transistor, the biasing circuit also provides reference voltage of 1.2V to the 𝑉𝑅𝐸𝐹 and 𝑉𝐢𝑀 pins. Both designs; the power supply circuit and biasing circuit must be done properly in order to hinder new interruption and produce a low noise voltage supply critically required for the successful testing of the IC. An external clock circuit is also necessary to provide pulse supply to another 16 pins of the IC. Finally to do the testing for the static characteristic of ADC, various dc voltages is fed to 𝑉𝐼𝑁+ and π‘‰πΌπ‘βˆ’ pin of the IC. The digital output word is displayed by the digital oscilloscope.
Contributor(s):
Khadijah Binti Hasbullah - Author
Primary Item Type:
Final Year Project
Identifiers:
Accession Number : 875003595
Barcode : 00003084287
Language:
English
Subject Keywords:
power supply circuit, dc biasingcircuit, clock circuit and digital oscilloscope to test the characteristic of an ADC IC; dc biasing block also designed together with this test circuit; biasing the transistor, the biasing circuit also provides reference voltage of 1.2V to the 𝑉𝑅𝐸𝐹 and 𝑉𝐢𝑀 pins. Both designs; the power supply circuit and biasing circuit must be done properly in order to hinder new interruption and produce a low noise voltage supply critically required for the successful testing of the IC
First presented to the public:
4/1/2010
Original Publication Date:
3/21/2018
Previously Published By:
Universiti Sains Malaysia
Place Of Publication:
School of Electrical & Electronic Engineering
Citation:
Extents:
Number of Pages - 113
License Grantor / Date Granted:
  / ( View License )
Date Deposited
2018-03-21 15:18:28.861
Date Last Updated
2019-01-07 11:24:32.9118
Submitter:
Nor Hayati Ismail

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Test circuit for adc ic testing / Khadijah Binti Hasbullah1 2018-03-21 15:18:28.861