W-CDMA (Bahagian Kod Jalur Lebar Capaian Berbilang) adalah sejenis
rangkaian popular selular 3G. Penerima-penerima wayarles untuk aplikasi W-CDMA
perlu mengesan dan menggandakan isyarat-isyarat masukan kuasa rendah tanpa
menambah banyak hingar. LNA lazimnya digunakan sebagai penguat peringkat pertama
dalam penerima. Keperluan prestasi tinggi dalam W-CDMA menjadi motivasi untuk
kajian kemungkinan teknologi CMOS digunakan untuk implementasi penguat hingar
rendah (LNA). Teknologi CMOS adalah menarik kerana ia memungkinkan penyepaduan
keseluruhan sistem pada satu cip. Projek ini memberi fokus kepada simulasi pascabentangan
terkelebet kaskod masukan berhujung tunggal menggunakan process CMOS
0.18μ. Beberapa teknik rekaan telah dilaporkan untuk tujuan tersebut. Teknik Kuasa
Terkekang Padanan Masukan Dan Hingar Serentak (PCSNIM) antara yang digunakan
dengan satu kapasitor tambahan, antara get-punca peranti semiconduktor serta
topologi kemerosotan punca induktif sebagai penamatan. Tambahan pula, teknik ini
membantu dalam padanan masukan pada satu cip. Hasil-hasil simulasi pra-bentangan
menunjukkan bahawa teknologi CMOS hanya memerlukan bekalan kuasa 0.6 manakala
mencapai gandaan kuasa, 14.8, pekali pantulan masukan,
11.47 , pekali pantulan keluaran, 21.84 , pengasingan balikan,
44.75 dan 2.0. Kelinearan berdasarkan Pintasan Titik
Masukan Tertib Ketiga 3 11.81 tentuluar pada 30 dan Titik
Mampatan Masukan 1 25.88. Pelepasan kuasa adalah 2.35._
W-CDMA (Wideband Code Division Multiple Access) is a type of popular 3G
cellular network. Wireless receivers for W-CDMA application need to be able to detect
and amplify incoming low-power signals without adding much noise. The most common
solution uses low noise amplifier (LNA) as the first stage in receiver. The strict
requirement of good blocks performance in the W-CDMA receiver has motivated studies
on feasibility of CMOS technology for the implementation of good noise performance in
the LNA. The advancement in the CMOS technology has made it possible to integrate the
whole system on a single chip. This project focused on designed and post-layout
simulation of single-ended folded cascode CMOS LNA using a standard 0.18 μm
fabrication process. In this project, the folded-cascode LNA was following the Power-
Constrained Simultaneous Noise and Input Matching (PCSNIM) technique with an
additional capacitor, connected from gate to source of a common source transistor
and employed inductive source degeneration termination. Furthermore, this technique
helps on-chip input matching. Pre-layout simulation results shows that CMOS technology
has the capability to achieve a 0.6 power supply while achieves a power gain
of 14.8 , input reflection coefficient, of 11.47 , output reflection
coefficient, of 21.84 , reverse isolation, of 44.75 and of 2.0 .
Linearity on Input Third-Order Intercept Point 3 is 11.81 extrapolated at
30 and Input 1 Compression Point is 25.9 . Total power
consumption is 2.35.
DESIGN AND POST LAYOUT SIMULATION OF THE SINGLE-ENDED FOLDED CASCODE LOW NOISE AMPLIFIER_ Tee Chee Keong_E3_2008_875002482_NI